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hv-bridge
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hv-bridge<\x> ddr5
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hyc2x DDR4 latency
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hycgood thing AMD has such large on-chip caches
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hv-bridge<\x> hyc, the timings are insanely high
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hv-bridge<\x> lol
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hv-bridge<\x> 4800 can be done in ddr4 when oc'd but nowhere those timings
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hv-bridge<\x> normally its like 19-27-27 for ddr4, this thing is 40-40-40
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hv-bridge<\x> but yeah thats oc, 4800 flat 40 seems where ddr5 will start on consumer desktops
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sech1same was with DDR3 vs DDR4 when DDR4 just got released
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hyctrue
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hv-bridge<\x> havent i shared ddr5's spec pdf here
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hv-bridge<\x> sech1: ddr4 started like 2133 when way back sandy era we already had dimms rated 2133, when ivy came dimms rated 2666++ happened, ddr3 ended around 3200 for some high end xmp kits with hynix ICs
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hv-bridge<\x> nowadays if we dont get another gen of ddr4, ddr4 will likely end on 5100 or 5300 xmp if gskill makes their 5300 bins public
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jcphamwhat's a hashvault?
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jcphami'm dumb
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jcphamoh it's a ppool
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jcpham5.243 kh/s
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jcphamYour Hashrate
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jcphami'm so poor