04:34:57 <hv-bridge> <\x> https://twitter.com/9550pro/status/1371647429779496962
04:35:01 <hv-bridge> <\x> ddr5
11:31:46 <hyc> 2x DDR4 latency
11:32:07 <hyc> good thing AMD has such large on-chip caches
11:49:06 <hv-bridge> <\x> hyc, the timings are insanely high
11:49:09 <hv-bridge> <\x> lol
11:49:24 <hv-bridge> <\x> 4800 can be done in ddr4 when oc'd but nowhere those timings
11:49:43 <hv-bridge> <\x> normally its like 19-27-27 for ddr4, this thing is 40-40-40
11:50:01 <hv-bridge> <\x> but yeah thats oc, 4800 flat 40 seems where ddr5 will start on consumer desktops
11:55:32 <sech1> same was with DDR3 vs DDR4 when DDR4 just got released
11:55:43 <hyc> true
11:56:49 <hv-bridge> <\x> havent i shared ddr5's spec pdf here
11:58:00 <hv-bridge> <\x> sech1: ddr4 started like 2133 when way back sandy era we already had dimms rated 2133, when ivy came dimms rated 2666++ happened, ddr3 ended around 3200 for some high end xmp kits with hynix ICs
11:58:46 <hv-bridge> <\x> nowadays if we dont get another gen of ddr4, ddr4 will likely end on 5100 or 5300 xmp if gskill makes their 5300 bins public
15:16:20 <jcpham> what's a hashvault?
15:16:24 <jcpham> i'm dumb
15:17:15 <jcpham> oh it's a ppool
15:17:44 <jcpham> 5.243 kh/s
15:17:45 <jcpham> Your Hashrate
15:17:53 <jcpham> i'm so poor