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hycnew AMD Milan family of Epyc server CPUs is finally available for sale
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hyc64 cores, 25% perf boost over Rome
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hv-bridge<\x> somebody ask sth to bench randomx
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hv-bridge<\x> :p
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hv-bridge<\x> no lower end sku this time though
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hv-bridge<\x> weird
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hv-bridge<\x> tho those are prolly like, to follow...
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hycyeah whatever fails binning
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hv-bridge<\x> theres some frequency optimized ones, but yeah, highest clock is on 8c, 4.10ghz turbo
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hv-bridge<\x> 2400$ for that, i guess if you really need octa channel ram and tons of pcie
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hv-bridge<\x> and yeah 256MB L3 lmao
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hycyou could run an entire Linux distro entirely on-chip
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hv-bridge<\x> yep
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hv-bridge<\x> no cache as ram on amd though but yeah maybe its possible
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sech1BIOS code does it though in the initial startup, before DDR4 is initialized
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sech1there are special MSRs that configure caching
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hv-bridge<\x> nah, no CAR on ryzen afaik, i heard this from coreboot devs
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sech1maybe it was bulldozer documentation
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hycthat sounds like an odd feature to omit, since it's been standard for years
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hv-bridge<\x> idk on epyc
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hv-bridge
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hv-bridge<\x> i think this is the talk aboutt that
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hv-bridge<\x> though i havent seen a ryzen coreboott bootlog, ive seen an intel one, yeah cache as ram happens, tthen it checks for mrc cache
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gingeropoloussweet. that means Rome will drop in price hopefully