17:14:06 <hyc> new AMD Milan family of Epyc server CPUs is finally available for sale
17:14:19 <hyc> 64 cores, 25% perf boost over Rome
17:15:09 <hv-bridge> <\x> somebody ask sth to bench randomx
17:15:11 <hv-bridge> <\x> :p
17:15:36 <hv-bridge> <\x> no lower end sku this time though
17:15:39 <hv-bridge> <\x> weird
17:15:54 <hv-bridge> <\x> tho those are prolly like, to follow...
17:16:12 <hyc> yeah whatever fails binning
17:17:56 <hv-bridge> <\x> theres some frequency optimized ones, but yeah, highest clock is on 8c, 4.10ghz turbo
17:18:33 <hv-bridge> <\x> 2400$ for that, i guess if you really need octa channel ram and tons of pcie
17:18:53 <hv-bridge> <\x> and yeah 256MB L3 lmao
17:19:26 <hyc> you could run an entire Linux distro entirely on-chip
17:19:42 <hv-bridge> <\x> yep
17:20:22 <hv-bridge> <\x> no cache as ram on amd though but yeah maybe its possible
17:24:51 <sech1> BIOS code does it though in the initial startup, before DDR4 is initialized
17:24:59 <sech1> there are special MSRs that configure caching
17:25:35 <hv-bridge> <\x> nah, no CAR on ryzen afaik, i heard this from coreboot devs
17:26:05 <sech1> maybe it was bulldozer documentation
17:26:07 <hyc> that sounds like an odd feature to omit, since it's been standard for years
17:26:07 <hv-bridge> <\x> idk on epyc
17:26:40 <hv-bridge> <\x> https://youtu.be/eyRsk8GU3OE?t=394
17:26:48 <hv-bridge> <\x> i think this is the talk aboutt that
17:27:21 <hv-bridge> <\x> though i havent seen a ryzen coreboott bootlog, ive seen an intel one, yeah cache as ram happens, tthen it checks for mrc cache
18:36:06 <gingeropolous> sweet. that means Rome will drop in price hopefully