<\x> xmrig.com/benchmark/7HeVKH

<\x> cezanne

<\x> cc sech1 @sech1

<\x> cdn.discordapp.com/attachments/7253…831/819440568911790090/4200_gb3.png

853 h/s/thread ?

<\x> seems like it

<\x> imc seems great but yeah, powerlimits seems low on this one, it acts like a mobile chip on a desktop the user says, but yeah its still a QS chip

ARM N1 review blog.cloudflare.com/arms-race-ampere-altra-takes-on-aws-graviton2

so the architecture supports up to 256MB L3 cache, current chips only implement 32MB

these server vendors don't seem to know what they're doing. and are ignoring the path AMD has very clearly laid out for the world to see

wassat, massive cache?

yes

AMD is doing well on that front. no one else really is doing it

y do you think that is? Is it expensive or hard to get that much cache on chip?

it is expensive, sure. costs real estate

majority of chip size is cache

and the larger the surface area, the higher the probability of defects. but well designed caches can workaround them