Didn’t the last CN variant have ASICs that were only discovered after the switch to Rx?

I guess by discovered you mean confirmed, was obvious both times that there were asics

at least to me

i dunno NickvanSaberhagn . CN-R seemed like it was holding - bitinfocharts.com/comparison/monero-hashrate.html

Gingeropolous: right it was steady I’m just saying I think via nonce analysis we discovered later there were FPGAs or ASICS on it

perhaps sech1 dived into it?

guess imma confusing CN-R with the earlier change

well the naming scheme was always a matter of confusion

I wouldn't mind a cn-heavy/xhv asic if anyone has one lying around :P

cn/r had ASICs in the end, ~10% of the network: reddit.com/r/Monero/comments/eqecqn…ghtr_is_mined_by_asics_or_fpgas_now

<sech1> 30 out of 300 mh/s which is not as bad as previous Cryptonight variants, so it was more resistant

sure, CN-R would have required a slightly more expensive ASIC

Big fire in OVH data centers in France travaux.ovh.net/?do=details&id=49484

sech1: i know.

Yep that’s what I was referring to

a phone with 18GB RAM arstechnica.com/gadgets/2021/03/the…am-two-usb-ports-crazy-rear-display

has the latest flagship snapdragon, 888

mine xmr on that while gaming

All these ARM CPUs lack cache. They better have 2 MB cache per core than 18GB RAM :D

Cortex-X1 is an interesting CPU, it can have up to 8 MB L3 (but not in snapdragon 888 though)

a cluster of 4xCortex-X1 and 8 MB L3 cache would make a nice and efficient RandomX capable CPU

indeed. might happen, if more ARM server designs spring up