00:30:52 Didn’t the last CN variant have ASICs that were only discovered after the switch to Rx? 00:51:17 I guess by discovered you mean confirmed, was obvious both times that there were asics 00:51:24 at least to me 01:22:33 i dunno NickvanSaberhagn . CN-R seemed like it was holding - https://bitinfocharts.com/comparison/monero-hashrate.html 01:23:45 Gingeropolous: right it was steady I’m just saying I think via nonce analysis we discovered later there were FPGAs or ASICS on it 01:24:15 perhaps sech1 dived into it? 01:24:42 guess imma confusing CN-R with the earlier change 01:26:10 well the naming scheme was always a matter of confusion 06:44:12 I wouldn't mind a cn-heavy/xhv asic if anyone has one lying around :P 07:20:26 cn/r had ASICs in the end, ~10% of the network: https://www.reddit.com/r/Monero/comments/eqecqn/cryptonightr_is_mined_by_asics_or_fpgas_now/ 07:22:17 30 out of 300 mh/s which is not as bad as previous Cryptonight variants, so it was more resistant 10:19:39 sure, CN-R would have required a slightly more expensive ASIC 13:03:08 Big fire in OVH data centers in France http://travaux.ovh.net/?do=details&id=49484 13:53:34 sech1: i know. 19:19:06 Yep that’s what I was referring to 19:43:47 a phone with 18GB RAM https://arstechnica.com/gadgets/2021/03/the-asus-rog-phone-5-has-18gb-of-ram-two-usb-ports-crazy-rear-display/ 19:44:45 has the latest flagship snapdragon, 888 19:45:24 mine xmr on that while gaming 19:58:40 All these ARM CPUs lack cache. They better have 2 MB cache per core than 18GB RAM :D 20:02:34 Cortex-X1 is an interesting CPU, it can have up to 8 MB L3 (but not in snapdragon 888 though) 20:04:02 https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging/3 20:07:20 a cluster of 4xCortex-X1 and 8 MB L3 cache would make a nice and efficient RandomX capable CPU 23:00:24 indeed. might happen, if more ARM server designs spring up