05:19:27 <hv-bridge> <\x> https://xmrig.com/benchmark/7HeVKH
05:19:29 <hv-bridge> <\x> cezanne
05:19:37 <hv-bridge> <\x> cc sech1 @sech1
05:24:17 <hv-bridge> <\x> https://cdn.discordapp.com/attachments/725316395428085831/819440568911790090/4200_gb3.png
11:53:44 <gingeropolous> 853 h/s/thread ?
12:12:50 <hv-bridge> <\x> seems like it
12:13:43 <hv-bridge> <\x> imc seems great but yeah, powerlimits seems low on this one, it acts like a mobile chip on a desktop the user says, but yeah its still a QS chip
21:36:24 <hyc> ARM N1 review https://blog.cloudflare.com/arms-race-ampere-altra-takes-on-aws-graviton2/
21:36:46 <hyc> so the architecture supports up to 256MB L3 cache, current chips only implement 32MB
21:37:26 <hyc> these server vendors don't seem to know what they're doing. and are ignoring the path AMD has very clearly laid out for the world to see
21:39:41 <gingeropolous> wassat, massive cache?
21:42:18 <hyc> yes
21:42:44 <hyc> AMD is doing well on that front. no one else really is doing it
21:46:53 <gingeropolous> y do you think that is? Is it expensive or hard to get that much cache on chip?
21:52:30 <hyc> it is expensive, sure. costs real estate
21:52:49 <hyc> majority of chip size is cache
21:53:48 <hyc> and the larger the surface area, the higher the probability of defects. but well designed caches can workaround them