well gonna need some data cleanup for that!

Had a long talk with a FPGA guy today who was convinced that RandomX could be added to a FPGA by arranging a set of CPUs on a single board and then adding a FPGA header above them. The FPGA could pass off to the CPUs the parts of the algorithm that are CPU necessary and then FPGA the rest. Is this a valid RandomX FPGA? What risk might this have for miner centralization?

I wonder what the "rest" is

But the rest sounds like it is describing a modern AMD cpu :P

"The FPGA could pass off to the CPUs the parts of the algorithm that are CPU necessary and then FPGA the rest. Is this a valid RandomX FPGA?" Short answer is no

I mean it's possible but would be slower if everything was done on CPUs :D

Technically FPGA could be used to find easy programs for CPU, but it matters only for the first of 8 RandomX programs

So let's say first program gets 20% faster on average (1 of 10 programs are), FPGA would need to do 10x more AES rounds to find it which it can do

This would result in the overall 2.5% speedup, but FPGA power draw will negate it anyway

sounds like they want to take a SIMD approach but the workload is actually MIMD so no, there is nothing to be gained there

aside from the logical difficulties, the practical issues are insurmountable. the FPGA would have to run multiple times faster than the CPUs to keep them all busy

and the communication channel btw FPGA and CPUs would have to be at least as fast as DDR memory bus

all of which would be ridiculously expensive

faster than memory bus

scratchpad is 2 MB and single RandomX hash reads 1 MB of data from memory

plus moving scratchpad back and forth will pollute CPU cache (L1 & L2)

what they're imagining has been the holy grail for supercomputing for several decades

Integrating small FPGA into each CPU core with access to all CPU caches would be advantageous though

what would it accomplish?

faster AES for example

and faster JIT

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