00:21:04 <gingeropolous> well gonna need some data cleanup for that!
02:49:30 <NickvanSaberhagn> Had a long talk with a FPGA guy today who was convinced that RandomX could be added to a FPGA by arranging a set of CPUs on a single board and then adding a FPGA header above them. The FPGA could pass off to the CPUs the parts of the algorithm that are CPU necessary and then FPGA the rest. Is this a valid RandomX FPGA? What risk might this have for miner centralization?
07:08:56 <Inge-> I wonder what the "rest" is
07:09:31 <Inge-> But the rest sounds like it is describing a modern AMD cpu :P
07:54:01 <sech1> "The FPGA could pass off to the CPUs the parts of the algorithm that are CPU necessary and then FPGA the rest. Is this a valid RandomX FPGA?" Short answer is no
07:54:32 <sech1> I mean it's possible but would be slower if everything was done on CPUs :D
07:56:25 <sech1> Technically FPGA could be used to find easy programs for CPU, but it matters only for the first of 8 RandomX programs
07:57:13 <sech1> So let's say first program gets 20% faster on average (1 of 10 programs are), FPGA would need to do 10x more AES rounds to find it which it can do
07:57:42 <sech1> This would result in the overall 2.5% speedup, but FPGA power draw will negate it anyway
14:51:32 <hyc> sounds like they want to take a SIMD approach but the workload is actually MIMD so no, there is nothing to be gained there
14:53:31 <hyc> aside from the logical difficulties, the practical issues are insurmountable. the FPGA would have to run multiple times faster than the CPUs to keep them all busy
14:53:49 <hyc> and the communication channel btw FPGA and CPUs would have to be at least as fast as DDR memory bus
14:54:05 <hyc> all of which would be ridiculously expensive
14:56:32 <sech1> faster than memory bus
14:56:53 <sech1> scratchpad is 2 MB and single RandomX hash reads 1 MB of data from memory
14:57:18 <sech1> plus moving scratchpad back and forth will pollute CPU cache (L1 & L2)
14:58:29 <hyc> what they're imagining has been the holy grail for supercomputing for several decades
14:58:29 <sech1> Integrating small FPGA into each CPU core with access to all CPU caches would be advantageous though
14:59:09 <hyc> what would it accomplish?
14:59:54 <sech1> faster AES for example
15:00:09 <sech1> and faster JIT
18:56:30 <gingeropolous> total miners 82218
18:56:38 <gingeropolous> minexmr.com 32.9