05:16:01 <gingeropolous> i wonder how long the road to 3 gh/s is gonna be
05:16:14 <gingeropolous> .c 1+1
05:16:18 <gingeropolous> no bot i guess
05:17:47 <gingeropolous> what was the spike from azure agan
05:18:32 <gingeropolous> 2.44 gh/s
05:18:41 <nioc> mebbe 600 MHz by themselves
05:19:10 <nioc> anybody who actually knows is sleeping so I took a guess
05:20:05 <gingeropolous> looks about right: https://bitinfocharts.com/comparison/monero-hashrate.html
05:20:33 <gingeropolous> it'd be the equivalent of 10k dual epyc miners, if those dual epycs can to 100 kh/s
05:20:36 <gingeropolous> *can do
05:20:52 <gingeropolous> so it could be a long road
05:22:56 <nioc> senile man strikes again \o/
11:48:29 <gingeropolous> well, i guess presumably at some point the infrastructure of the large pools will hit its limit
11:48:55 <gingeropolous> and pool ops will either have to upgrade / add more infa, or find a way to encourage ppl to move
11:49:02 <gingeropolous> because performance could be degraded for everyone
12:26:42 <hv-bridge> <\x> lol
17:11:14 <gingeropolous> total miners 78170
17:11:18 <gingeropolous> minexmr.com 32.7
17:38:50 <Inge-> unknown isn't that big either
18:52:32 <midipoet> OMG I forgot about the bullet catching drones
18:53:10 <midipoet> Also, wasn't there a whole company. What was it called? They wanted to mine in fridges and ovens
18:53:24 <midipoet> Kristy, I think, right?
18:53:51 <moneromooo> Kristy Leigh Minehan (spelling might be off a tad).
18:54:41 <midipoet> was that also bat shit crazy or legit? The idea was IoT mining devices, which didn't seem too off the wall.
18:57:43 <Inge-> reading scrollback midipoet ? :D
19:15:33 <midipoet> maybe
21:30:51 <lkcl_> scrolling back to the bit about RAM: OpenCAPI, OpenHMI and Gen-Z are all designed to be 3D stacked memory for GPU and Supercomputers
21:31:20 <lkcl_> and AMD has started doing chiplets for multi-core SMP
21:32:33 <lkcl_> putting 2+2 together to make 5, it's not outside the realm of possibility that every-day computers / GPUs end up with insanely-fast multi-chip NoC'd DRAM access
21:33:58 <lkcl_> (translation) a large batch of DRAM ICs, which gives great throughput, backed up by a Network-on-Chip that routes through and gives general high-performance access
21:34:45 <lkcl_> somewhere in 5-6 years i am planning to implement precisely and exactly that (if another fabless semi company doesn't do it before then)
21:35:41 <lkcl_> and i know of at least one person looking to design an alt-currency ASIC-based-on-GPU with the same type of 3D-stacked layout
21:36:13 <lkcl_> multiple 20 gigabit SERDES to multiple DRAMs *well* in excess of what is "traditionally" done in any CPU or GPU
21:37:23 <lkcl_> these types of designs will literally eat RandomX for breakfast
21:45:10 <Inge-> go for it
22:01:55 <sech1> DRAM access is not a bottleneck in RandomX even just with well-tuned DDR4, there's no need for much faster RAM
22:02:21 <sech1> RandomX is not just about memory access lkcl_ but good luck anyway :P
22:19:04 <Inge-> it would probably eat CN for dinner
22:27:07 <hyc> CN was toast 3 years ago tho
22:27:21 <hyc> no challenge there