15:55:47 <kinghat[m]> zen 3 https://youtu.be/iuiO6rqYV4o
16:06:17 <sech1> ye, watching it
16:46:57 <Inge-> 20% ipc increase. maybe faster?
18:02:23 <hyc> cool stuff
18:12:12 <sech1> it would be fun if they change MSR registers and MSR mod doesn't work and no docs available :D
18:17:21 <selsta> how much do gain with these MSR mods?
18:23:44 <sech1> 7-8%
18:24:32 <Inge-> I got less :/
18:24:37 <sech1> it works on all Ryzens and registers are the same, so fingers crossed
18:29:38 <hyc> I doubt they'd change
18:31:20 <sech1> looks like they did some changes in prefetchers, so maybe something changed
18:33:41 <hyc> change register layout? unlikely.
18:33:47 <hyc> change flags values? maybe
18:34:11 <Inge-> changed how the L3 cache is organized/Accessed
18:34:20 <Inge-> since a single core can now access 32MB of L3