07:56:42 <sech1> hyc tevador It's been more than 4 months since RandomX went live, do you have any estimates how fast ARM-based SoC tuned for RandomX (caches, memory) can be developed?
14:43:46 <gingeropolous> sech1, are you observing any abnormal network behavior?
14:45:07 <sech1> No
14:47:45 <sech1> It was more a theoretical question
16:47:33 <hyc> there are ARM SoCs using LPDDR4 now. still the main complexity is a large enough on-chip cache, and its controller
16:47:51 <hyc> ARM's off-the-shelf stuff won't handle that, so those must be independently designed
16:48:10 <hyc> and very few companies have the license to do so. Qualcomm is one, Apple probably another
16:48:15 <hyc> Samsung
20:00:05 <gingeropolous> i'll also pose a theoretical question. If we were to consider optimizations for randomx re: CPU binding, what would they be?
20:33:06 <sech1> For x86 CPUs? AVX (4x64 bit floats) instead of SSE (2x64 bit) is the first obvious change
21:08:34 <hyc> binding to just x86 is not a good move tho